Title :
Testing the unidimensional interconnect architecture of symmetrical SRAM-based FPGA
Author :
Renovell, M. ; Faure, P. ; Prinetto, P. ; Zorian, Y.
Author_Institution :
LIRMM-UM2, Montpellier, France
Abstract :
This paper proposes a new and original solution to test the unidimensional interconnect architecture of a RAM based FPGA by exploring the specific properties of these blocks. The method to find a reduced set of configurations is proposed and the sequence of test vectors required for each configuration is given
Keywords :
SRAM chips; field programmable gate arrays; integrated circuit interconnections; integrated circuit testing; logic testing; FPGA configurations; reduced configuration set; symmetrical SRAM-based FPGA; test vector sequence; unidimensional interconnect architecture testing; Field programmable gate arrays; Integrated circuit interconnections; Logic design; Logic testing; Manufacturing; Programmable logic arrays; Random access memory; Reconfigurable logic; Switches; Wires;
Conference_Titel :
Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on
Conference_Location :
Christchurch
Print_ISBN :
0-7695-1453-7
DOI :
10.1109/DELTA.2002.994634
