• DocumentCode
    2402503
  • Title

    The 3-D computer

  • Author

    Little, M.J. ; Etchells, R.D. ; Grinberg, J. ; Laub, S.P. ; Nash, J.G. ; Yung, M.W.

  • Author_Institution
    Hughes Res. Lab., Malibu, CA, USA
  • fYear
    1989
  • fDate
    3-5 Jan 1989
  • Firstpage
    55
  • Lastpage
    64
  • Abstract
    The 3-D Computer is an implementation of a cellular array processor. Two technologies which make possible massive numbers of communication channels both between silicon wafers and through them have been developed. A parallel processor (single-instruction-multiple-data stream cellular array processor) has been designed and built to demonstrate the potential of this technological approach. While the 3-D computer which has been built and operated is a small-scale implementation relative to the long-term aims of this technology, it is nevertheless an extremely powerful computer. The current feasibility demonstration 3-D Computer is a 32×32 array of processors partitioned over five wafers stacked one on top of another. The throughput of this machine is >600 million operations per second with a 10-MHz clock, while the projected throughput of a full-scale machine is >100 billion operations per second, again with a 10-MHz clock
  • Keywords
    VLSI; cellular arrays; microprocessor chips; parallel processing; 10 MHz; 3-D Computer; cellular array processor; communication channels; parallel processor; single-instruction-multiple-data stream; throughput; wafers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Wafer Scale Integration, 1989. Proceedings., [1st] International Conference on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    0-8186-9901-9
  • Type

    conf

  • DOI
    10.1109/WAFER.1989.47536
  • Filename
    47536