Path-oriented test data generation of behavioral VHDL description

The validation of HDL descriptions before their synthesis is one of the principal problems related to the top-down design process of complex circuits. This task can be accomplished according two approaches: formal verification or simulation based validation. Because formal verification, in spite of recent progress, is only feasible for small descriptions, simulation is still the best way to test hardware design. One of the main problems of such approach is to generate test vectors in order to verify design specifications. We think that high level HDL description represents a new source of information about the circuit which may be useful in test data generation field. The approach presented in this paper borrows techniques used successfully in software testing area for test vectors generation. This paper focus on a path-oriented test data generator