DocumentCode :
2402834
Title :
Random pattern testability of the open defect detection method using application of time-variable electric field
Author :
Yotsuyanagi, Hiroyuki ; Hashizume, Masaki ; Iwakiri, Taisuke ; Ichimiya, Masahiro ; Tamesada, Takeomi
Author_Institution :
Dept. of Electr. & Electron. Eng., Tokushima Univ., Japan
fYear :
2002
fDate :
2002
Firstpage :
387
Lastpage :
391
Abstract :
In this paper, random pattern testability of the open defect defection method is discussed. In the test method, time-variable electric field is applied from the outside of ICs so as to vary the voltage at floating nodes caused by a defect. To detect opens the excessive supply current caused by the applied electric field is measured. The test pattern requirements for detecting opens are shown. The fault coverage for open defects is calculated for benchmark circuits. The experimental results shows random pattern can be effectively utilized for the test method even if it cannot attain high fault coverage for stuck-at-faults
Keywords :
CMOS logic circuits; automatic test pattern generation; electric fields; fault simulation; time-varying systems; CMOS; benchmark circuits; excessive supply current; fault coverage; floating nodes; open defect defection method; opens detection; random pattern testability; stuck-at faults; test pattern requirements; time-variable electric field; CMOS logic circuits; Circuit faults; Circuit testing; Current measurement; Current supplies; Electric variables measurement; Electrical fault detection; Electronic equipment testing; Logic testing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on
Conference_Location :
Christchurch
Print_ISBN :
0-7695-1453-7
Type :
conf
DOI :
10.1109/DELTA.2002.994656
Filename :
994656
Link To Document :
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