A functional approach to test cascaded BCD counters

Author

Peretti, Gabriela ; Romero, Eduardo ; Salvático, Franco ; Marqués, Carlos

Author_Institution

Electron. & Control Res. Group, Nat. Univ. of Technol., Cordoba, Argentina

fYear

2002

fDate

2002

Firstpage

408

Lastpage

412

Abstract

This work presents an off-line Built-In Self-Test for timing systems based on synchronous BCD counters. We adopt for this case study a functional approach, exploiting the functional characteristics of the modules in the system for test pattern generation. Different alternatives for test sequences, simulation and experimental results are shown. Fault coverage of 95% and 100% are obtained under different test sequences. The test time scales up linearly with the number of cascaded counters, and the hardware overhead becomes less significant as the number of counters increases

Keywords

built-in self test; counting circuits; fault simulation; field programmable gate arrays; integrated circuit testing; logic testing; timing circuits; FPGA; binary coded decimal counters; cascaded BCD counters; fault coverage; functional approach; hardware overhead; module functional characteristics; off-line BIST; simulation; structural single stuck-at fault model; synchronous BCD counters; test pattern generation; test sequences; timing systems; Automatic testing; Built-in self-test; Circuit testing; Control systems; Counting circuits; Electronic equipment testing; Radiation detectors; System testing; Test pattern generators; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on

Conference_Location

Christchurch

Print_ISBN

0-7695-1453-7

Type

conf

DOI

10.1109/DELTA.2002.994660

Filename

994660