Title :
Recursive layout generation
Author :
Monier, Louis M. ; Haddad, Ramsey W. ; Dion, Jeremy
Author_Institution :
Western Res. Lab., Digital Equipment Corp., Palo Alto, CA, USA
Abstract :
We present a recursive method for generating layout for VLSI chips based on integrating layout directives in the netlist description. The method allows seamless integration of hand-drawn and synthesized layout, so that hand layout need only be used where the increase in density is justified. Layout is generated automatically with predictable results; small changes in the source result in small changes of the overall layout. The system is versatile enough to build dense BiCMOS VLSI microprocessor chips automatically
Keywords :
BiCMOS digital integrated circuits; VLSI; circuit layout CAD; logic CAD; microprocessor chips; VLSI chips; dense VLSI; hand-drawn layout; layout directives; microprocessor chips; netlist description; overall layout; recursive layout generation; seamless integration; synthesized layout; Circuit synthesis; Computer languages; Delay; Equations; Hardware; Laboratories; Logic design; Microprocessor chips; Programmable logic arrays; Wire;
Conference_Titel :
Advanced Research in VLSI, 1995. Proceedings., Sixteenth Conference on
Conference_Location :
Chapel Hill, NC
Print_ISBN :
0-8186-7074-9
DOI :
10.1109/ARVLSI.1995.515619
