Abstract :
Summary form only given. Conventional CMOS technology will face difficulties in the sub-0.1 μm, sub-1 V region. Random-modulation CMOS, which assigns multiple threshold levels in the same block through the use of sophisticated CAD tools, will emerge as a key technology in this new regime. Beginning with this first step, the era of "complex CMOS", which requires complicated design elaborations and operating control, is predicted to begin. This key change will open up opportunities for new methodologies and CAD tools. Another major change in trend will be the shift in System-on-Chip design methodology from being processor-centric to either memory-centric or communication-centric, depending on the application. In the former case, nanostructured memory technology will be a key innovation, which requires completely new design expertise, including quantum physics. In the latter case, real IP reuse is the key, which will be enabled by a new specification language, such as the Object Wrapper language. Our efforts to standardize this new language and its design methodology are also introduced
Keywords :
CMOS integrated circuits; circuit CAD; integrated circuit design; specification languages; 0.1 micron; 1 V; CAD tools; CMOS technology; LSI design; Object Wrapper language; complex CMOS; design methodologies; multiple threshold levels; nano-structured memory technology; quantum physics; random-modulation CMOS; real IP reuse; specification language; sub-0.1 μm sub-1 V region; system-on-chip design methodology; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Design automation; Design methodology; Laboratories; Large scale integration; Logic circuits; Physics; Very large scale integration;
