Title :
Capacitor-less 1-transistor DRAM
Author :
Fazan, P. ; Okhonin, S. ; Nagoga, M. ; Sallese, J.M. ; Portmann, L. ; Ferrant, R. ; Kayal, M. ; Pastre, M. ; Blagojevic, M. ; Borschberg ; Declercq, M.
Author_Institution :
LEG, Swiss Fed. Inst. of Technol., Lausanne, Switzerland
Abstract :
We review the current status of the 1T-DRAM development, illustrate how this concept can be extended to fully depleted (FD) SOI, and demonstrate a first circuit application. A memory circuit area reduction of 3 to 10 times can be achieved when compared to DRAM or SRAM reference circuits respectively.
Keywords :
CMOS memory circuits; DRAM chips; silicon-on-insulator; FD SOI CMOS; capacitor-less 1T DRAM; fully depleted FD SOI; memory circuit area reduction; CMOS memory integrated circuits; DRAM chips; Silicon on insulator technology;
Conference_Titel :
SOI Conference, IEEE International 2002
Print_ISBN :
0-7803-7439-8
DOI :
10.1109/SOI.2002.1044398
