Tutorial on modeling parasitic coupling effects in reliability verification

Summary form only given. As technology scaling continues in the deep sub-micron domain, interconnect parasitics have become dominant in determining chip performance and functionality. R(L)C parasitics play a major role in chip performance, functionality and signal integrity. In addition, parasitics have significant impact on chip reliability due to electromigration (EM), timing dependent dielectric breakdown (TDDB) and channel hot carrier (CHC) effects. This tutorial covers several aspects of interconnect modeling from chip reliability perspective. Special emphasis is made on importance of modeling parasitic coupling in reliability analysis. A comparative study of coupled and decoupled interconnect modeling is discussed with simple examples and real life circuits