Application specific embedded 8-Port SRAM with simultaneous 256-bit data accessibility

An embedded eight-port, 32-word×6 Mbit SRAM is designed by 3.3V, 0.65 μm CMOS technology. The bit lines of the SRAM are connected on column switching multiplexer array (CSMA) to enable eight-32 bit data manipulation at a time. We propose a pulse generator with self-XORs, and a reset scheme for control signals. We use both rising and falling edges, so access time is 15 ns. The proposed SRAM architecture provides 256-bit simultaneous access in horizontal or vertical data streams with adjacent or even pixel accessibility for DCT operation, and operates on 100 MHz at 3.3 V