A complete environment for global architecture synthesis

An architecture synthesis environment oriented towards VLSI image processing systems is presented. The new method consists in synthesizing simultaneously data-path and control part of the architecture. The whole environment allows the description of the algorithm and its emulation on a powerful highly parallel dedicated computer. Results of the emulation are used by the synthesis tools. The internal description of the architecture is a linked data-flow/control flow graph. During scheduling phase a regularity measure of the data-flow graph is used to minimize control complexity. The architecture of an image processing algorithm synthesized by means of this environment is shown