Integrated memory array processor: A prototype VLSI and a real-time vision system

Author

Fujita, Yoshihiro ; Yamashita, Nobuyuki ; Okazaki, Shin ´ichiro

Author_Institution

NEC Corp., Kawasaki, Kanagawa, Japan

fYear

1993

fDate

15-17 Dec 1993

Firstpage

82

Lastpage

91

Abstract

The authors describe the architecture and performance of a real-time vision system (RVS) and its use of an integrated memory array processor (IMAP) prototype LSI. This LSI integrates eight 8 bit processors and a 144 Kbit SRAM on a single chip. The RVS was developed using 64 IMAP prototype LSIs connected in series in a 512 processor system configuration. A host workstation can access memory on the IMAP prototype LSIs directly through a random access port. RVS peformance is shown in real-time road image processing and in real-time face detection as well as in low level image processing algorithms, such as filtering, histograms, discrete cosine transform (DCT), and rotation. The RVS image processing is shown to be much faster than the video rate

Keywords

SRAM chips; discrete cosine transform; filtering; histograms; host workstation; integrated memory array processor; low level image processing algorithms; random access port; real-time face detection; real-time road image processing; real-time vision system; rotation; Discrete cosine transforms; Image processing; Large scale integration; Machine vision; Prototypes; Random access memory; Real time systems; Roads; Very large scale integration; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Architectures for Machine Perception, 1993. Proceedings

Conference_Location

New Orleans, LA

Print_ISBN

0-8186-5420-1

Type

conf

DOI

10.1109/CAMP.1993.622461

Filename

622461