DocumentCode
2406483
Title
An adaptive interconnect-length driven placer
Author
Tsai, Chi-Ming ; Kuo, Kun-Tien ; Hong, Chyi-Hui ; Lin, Rung-Bin
Author_Institution
Dept. of Comput. Eng. & Sci., Yuan-Ze Univ., Chung-li, Taiwan
fYear
2002
fDate
2002
Firstpage
393
Lastpage
398
Abstract
An adaptive interconnect-length driven standard cell placer (ILDP) is developed The length bound for each source-sink pair is employed to direct the placement Of each cell during recursive min-cut partitioning. Global migration, gate resizing, and buffer insertion are performed to make length bounds easier to satisfy. Bound re-computation is dynamically invoked to generate more realizable bounds based on the current partial placement. ILDP is integrated into a commercial tool set. Experimental results show more than 20% delay reduction can be achieved for some MCNC benchmark circuits
Keywords
VLSI; cellular arrays; circuit layout CAD; delays; high level synthesis; integrated circuit interconnections; integrated circuit layout; network topology; adaptive standard cell placer; buffer insertion; commercial tool set; detailed placement; gate resizing; global migration; global placer; interconnect-length driven standard cell placer; length bound; min-cut partitioning; multi-pin net topology; net-length bound generator; recursive min-cut partitioning; source-sink pair; standard cell placement; timing model; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location
Bangalore
Print_ISBN
0-7695-1441-3
Type
conf
DOI
10.1109/ASPDAC.2002.994953
Filename
994953
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