A 1-V cyclic ADC using FD-SOI sample/hold circuits for sensor networks

Summary form only given. Recently, there has been much interest in sensor network systems that gather various analog signals, such as vital signs or environmental information, and that are connected to each other by a network In those systems, as there are huge number of sensing nodes, it is important that they are small and low power. To achieve this, the ADC, a key component in the node, should be small and operate at a supply voltage below 1 V. This would reduce power directly. Moreover, the ADC must be able to handle various signals, the frequencies of which range from several ten Hz to several kHz. We have developed a cyclic ADC using 0.2 μm CMOS/SOI technology. The proposed FD-SOI circuit achieves the operation at the supply voltage of 1 V or less, and can handle the sampling frequency ranging from 8 Sps to 8 kSps.