A voltage reference compatible with standard SOI CMOS processes and consuming 1 pA to 50 nA from room temperature up to 300°C

Author

Adriaensen, S. ; Dessard, V. ; Flandre, D.

Author_Institution

Microelectron. Lab., Univ. Catholiyue de Louvain, Louvain-la-Neuve, Belgium

fYear

2002

fDate

7-10 Oct 2002

Firstpage

130

Lastpage

131

Abstract

Summary form only given. We have presented a new and simple implementation of a voltage reference, based on an optimal standard SOI process mask use and a new architecture. The voltage drift over temperature is similar to standard references implementation while the power consumption and the chip area are drastically reduced. Additional threshold voltages can be obtained at no cost on most SOI processes and can be even more exploited for their usefulness in analog applications. Moreover, intrinsic MOSFETs, having better matching properties compared to doped devices, are of a great utility for critical analog blocks.

Keywords

CMOS analogue integrated circuits; low-power electronics; reference circuits; silicon-on-insulator; 1 pA to 50 nA; 20 to 300 C; Si; analog applications; chip area reduction; critical analog blocks; fully-depleted SOI process; intrinsic MOSFETs; partially-depleted SOI process; photolithographic masks; power consumption reduction; standard SOI CMOS processes; threshold voltages; ultra-low power applications; voltage reference; CMOS analog integrated circuits; Silicon on insulator technology;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, IEEE International 2002

Print_ISBN

0-7803-7439-8

Type

conf

DOI

10.1109/SOI.2002.1044448

Filename

1044448