VLSI implementation of 2-D DWT/IDWT cores using 9/7-tap filter banks based on the non-expansive symmetric extension scheme

This paper presents architectures and scheduling algorithms for the 2-D Discrete Wavelet Transform (DWT) and the Inverse Discrete Wavelet Transform (IDWT) using 9/7-tap filter banks based on the Non-expansive Symmetric Extension (NSE) scheme that reduces distortion at boundaries of the reconstructed image. The hardware has been implemented for image blocks of size 32×32 pixels, up to third level of transform, and cuts down the power consumption at the architecture level by incorporating three techniques, viz., Canonic Sign Digit (CSD) and common subexpression sharing technique, Gray code addressing mode and resource sharing. The implementation has been tested using 0.35 μm (three metal) technology by simulation at functional, circuit and physical levels. The performance measures of implementation, viz., area, memory requirement, speed and power have been evaluated