• DocumentCode
    24070
  • Title

    NBTI and Leakage Reduction Using ILP-Based Approach

  • Author

    Ing-Chao Lin ; Kuan-Hui Li ; Chia-Hao Lin ; Kai-Chiang Wu

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • Volume
    22
  • Issue
    9
  • fYear
    2014
  • fDate
    Sept. 2014
  • Firstpage
    2034
  • Lastpage
    2038
  • Abstract
    We propose an integer linear programming-based formulation to improve the effectiveness of the transmission gate-based technique intended to reduce negative-bias temperature instability and leakage power consumption. We also propose a virtual input pin technique to improve leakage reduction and use path sensitization to reduce area overhead. Simulation results show that combining these techniques can achieve >51.18% delay improvement and 63.34% leakage power improvement with only 2.31% area overhead.
  • Keywords
    MOSFET; integer programming; linear programming; negative bias temperature instability; ILP-based approach; NBTI; area overhead reduction; integer linear programming-based formulation; leakage power consumption; leakage reduction; negative-bias temperature instability reduction; pMOS transistor; path sensitization; transmission gate-based technique; virtual input pin technique; Degradation; Delays; Integrated circuit modeling; Logic gates; Optimization; Vectors; Very large scale integration; Aging mitigation; integer linear programming (ILP); leakage reduction; negative-bias temperature instability (NBTI); virtual pin; virtual pin.;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2013.2280651
  • Filename
    6607241