Title :
VHDL as a modeling-for-testability tool
Author :
Miczo, Alexander
Author_Institution :
ExperTest Inc., Mountain View, CA, USA
fDate :
Feb. 26 1990-March 2 1990
Abstract :
A number of design methodologies have emerged in recent years to facilitate the testing of digital circuits. These methodologies advocate the use of additional circuitry to enhance controllability and observability of internal circuit nodes. The author takes a slightly different approach to testing by examining the impact of information on the test problem. VHDL circuit descriptions are used.<>
Keywords :
circuit CAD; digital integrated circuits; logic CAD; logic circuits; logic testing; specification languages; VHDL circuit descriptions; controllability; design methodologies; digital circuit testing; digital circuits; modeling-for-testability; observability; testing; Circuit synthesis; Circuit testing; Design engineering; Hardware design languages; Integrated circuit interconnections; Integrated circuit testing; LAN interconnection; Logic design; Logic testing; Registers;
Conference_Titel :
Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-2028-5
DOI :
10.1109/CMPCON.1990.63716
