DocumentCode
2407481
Title
High speed, low power, low voltage ROMs
Author
Padoan, S. ; Boni, A.
Author_Institution
Parma Univ., Italy
fYear
1997
fDate
12-13 Sep 1997
Firstpage
18
Lastpage
21
Abstract
Both classical and novel bipolar differential ROM architectures are discussed with respect to the reduction of power consumption and supply voltages. Analytical relationships highlight the limitations of each architecture
Keywords
bipolar memory circuits; memory architecture; read-only storage; bipolar differential ROM architectures; high speed ROMs; low power operation; low voltage operation; power consumption reduction; supply voltage reduction; Batteries; Circuits; Differential amplifiers; Energy consumption; Frequency; Low voltage; Power amplifiers; Power supplies; Read only memory; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Analog and Mixed IC Design, 1997. Proceedings., 1997 2nd IEEE-CAS Region 8 Workshop on
Conference_Location
Baveno
Print_ISBN
0-7803-4240-2
Type
conf
DOI
10.1109/AMICD.1997.637184
Filename
637184
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