A wafer-scale architecture for artificial intelligence

The architecture presented exploits the advantages of wafer-scale integration technology and has a defect-tolerant scheme to overcome silicon defects. It is in principle a two-dimensional array that is suited to process semantic network knowledge bases. The defect-tolerance approach is based on a combination of hardware redundancy and robust algorithms run on the architecture. The application that is presented here is the scene labeling that is used in computer vision. Due to the robustness of the scene labeling algorithms the machine can tolerate some hardware faults at run time