SSC-a tool for the synthesis of testable sequential machines

A new CAD system, called SSC, is presented for the design and test of finite-state machines (FSMs). SSC utilizes a controlled design environment to simplify the logic synthesis and verification process. SSC utilizes a high-level structured input description where the state sequencing information is implicit in the specification. It is demonstrated that synthesis for testability and test generation depend on the type of state assignment adopted. SSC offers flexibility of choice in the synthesis of FSMs. It is shown that this flexibility is important because each of the state assignment options in SSC is tailored for a specific FSM structure. This enhances the performance of the final product as measured by silicon area, speed, and testability.<>