Shared multiplier design of a digital filter on a high-temperature FPGA module

This paper outlines the design of a space-efficient digital filter for use in high-temperature FPGA applications. It presents an implementation of a Butterworth filter design using VHDL: shared multiplier. It outlines the main signals and states used in the design. The shared multiplier design uses a single multiplier for each multiplication in the equation. The design is the smallest of the three. The results obtained by implementing the design on a FPGA are also presented. The shared multiplier approach is efficient in terms of demand of space on the FPGA