• DocumentCode
    2409623
  • Title

    A partition-based approach for identifying failing scan cells in scan-BIST with applications to system-on-chip fault diagnosis

  • Author

    Liu, Chunsheng ; Chakrabarty, Krishnendu

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
  • fYear
    2003
  • fDate
    2003
  • Firstpage
    230
  • Lastpage
    235
  • Abstract
    We present a new partition-based fault diagnosis technique for identifying failing scan cells in a scan-BIST environment. This approach relies on a two-step scan chain partitioning scheme. In the first step, an interval-based partitioning scheme is used to generate a small number of partitions, where each element of a partition consists of a set of scan cells. In the second step, additional partitions are created using an earlier-proposed random-selection partitioning method. Two-step partitioning leads to higher diagnostic resolution than a scheme that relies only on random-selection partitioning, with only a small amount of additional hardware. The proposed scheme is especially suitable for a system-on-chip (SOC) composed of multiple embedded cores, where test access is provided by means of a TestRail that is threaded through the internal scan chains of the embedded cores. We present experimental results for the six largest ISCAS-89 benchmark circuits and for two SOCs crafted from some of the ISCAS-89 circuits.
  • Keywords
    boundary scan testing; built-in self test; fault diagnosis; logic partitioning; logic simulation; logic testing; system-on-chip; TestRail test access; diagnostic resolution; failing scan cell identification; interval-based partitioning; multiple embedded core SOC; partition-based fault diagnosis technique; random-selection partitioning method; scan-BIST; system-on-chip fault diagnosis; two-step scan chain partitioning scheme; Application software; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Failure analysis; Fault diagnosis; Hardware; System testing; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition, 2003
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-1870-2
  • Type

    conf

  • DOI
    10.1109/DATE.2003.1253613
  • Filename
    1253613