Instruction set emulation for rapid prototyping of SoCs

Author

Schnerr, Jürgen ; Haug, Gunter ; Rosenstiel, Wolfgang

Author_Institution

FZI Forschungszentrum Informatik, Karlsruhe, Germany

fYear

2003

fDate

2003

Firstpage

562

Lastpage

567

Abstract

In this paper the application of Instruction Set Emulation (ISE) for rapid prototyping of SoCs is presented. The emulation works in a way that both the software and the hardware behaviour of the emulated processor core is reproduced cycle accurately. This requires the use of hardware and software components. The hardware component consists of a board containing a VLIW processor and FPGAs. The software component is an instruction set simulator of the core running on the VLIW processor. The FPGAs are used for emulating the SoC bus of this processor core. This way the simulation of an instruction set of a processor core has been extended to a real emulation of this core that can be used for rapid prototyping.

Keywords

circuit CAD; circuit simulation; instruction sets; integrated circuit design; integrated circuit modelling; synchronisation; system-on-chip; virtual machines; FPGAs; SoC bus; SoC prototyping; VLIW processor; core instruction set simulator; emulated processor core; instruction set emulation; rapid prototyping; Application software; Emulation; Field programmable gate arrays; Hardware; Prototypes; Software prototyping; Software systems; System testing; VLIW; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2003

ISSN

1530-1591

Print_ISBN

0-7695-1870-2

Type

conf

DOI

10.1109/DATE.2003.1253668

Filename

1253668