Title :
RTL test pattern generation for high quality loosely deterministic BIST
Author :
Santos, M.B. ; Fernandes, J.M. ; Teixeira, I.C. ; Teixeira, J.P.
Author_Institution :
IST / INESC-M, Lisboa, Portugal
Abstract :
High quality Built-In Self Test (BIST) needs to efficiently tackle the coverage of random-pattern-resistant (r.p.r) defects. Several techniques have been proposed to cover r.p.r faults at logic level, namely, weighted pseudo-random and mixed-mode. In mixed-mode test pattern generation (TPG) techniques, deterministic tests are added to pseudorandom vectors to detect r.p.r. faults. Recently, a RTL mixed-mode TPG technique has been proposed to cover r.p.r defects, the mask-based BIST technique. The purpose of this paper is to present mask-based BIST TPG improvements, namely in two areas: RTL estimation of the test length to be used for each mask in order to reach high Defects Coverage (DC), and the identification of an optimum mask for each set of nested RTL conditions. Results are used to predict the number of customized vectors for each mask of one ITC´99 benchmark module.
Keywords :
automatic test pattern generation; built-in self test; fault simulation; integrated circuit testing; logic testing; optimisation; probability; system-on-chip; ATPG; IP cores; RTL estimation; RTL test pattern generation; SoC cores; customized vectors; defect coverage; high quality BIST; intellectual property cores; loosely deterministic BIST; mask-based BIST technique; mixed-mode TPG technique; nested RTL conditions; optimum mask; random-pattern-resistant defects; test length estimation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Logic testing; Product development; System-on-a-chip; Test pattern generators; Vectors;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
Print_ISBN :
0-7695-1870-2
DOI :
10.1109/DATE.2003.1253734