A unified approach for SoC testing using test data compression and TAM optimization

Author

Iyengar, Vikram ; Chandra, Anshuman ; Schweizer, Sharon ; Chakrabarty, Krishnendu

Author_Institution

IBM Microeletronics, Essex Junction, VT, USA

fYear

2003

fDate

2003

Firstpage

1188

Lastpage

1189

Abstract

We integrate for the first time test access mechanism (TAM) optimization and test data compression into a single test methodology. We show how an integrated test architecture based on TAMs and test data decoders can be designed The proposed approach offers considerable savings in test data volume and testing time. Two case studies using the integrated test architecture are presented.

Keywords

automatic test equipment; data compression; decoding; integrated circuit testing; optimisation; system-on-chip; ATE; SoC testing; TAM optimization; integrated test architecture; test access mechanism optimization; test data compression; test data decoders; test data volume; test methodology; testing time; Benchmark testing; Circuit testing; Costs; Decoding; Manufacturing; Microelectronics; Optimization methods; System testing; System-on-a-chip; Test data compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2003

ISSN

1530-1591

Print_ISBN

0-7695-1870-2

Type

conf

DOI

10.1109/DATE.2003.1253794

Filename

1253794

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2413293