• DocumentCode
    2414232
  • Title

    Embedded split-gate flash memory with silicon nanocrystals for 90nm and beyond

  • Author

    Chindalore, Gowrishankar ; Yater, Jane ; Gasquet, Horacio ; Suhail, Mohammed ; Kang, Sung-Taeg ; Hong, Cheong Min ; Ellis, Nicole ; Rinkenberger, Glenn ; Shen, James ; Herrick, Matthew ; Malloch, Wendy ; Syzdek, Ronald ; Baker, Kelly ; Chang, Ko-Min

  • Author_Institution
    Technol. Solutions Organ., Freescale Semicond., Inc., Austin, TX
  • fYear
    2008
  • fDate
    17-19 June 2008
  • Firstpage
    136
  • Lastpage
    137
  • Abstract
    We present a split-gate based NOR flash memory array with silicon nanocrystals as the storage medium. 128 KB memory arrays have been evaluated with this technology and the results presented here show a nanocrystal memory that has been demonstrated to achieve a minimum 1.5 V operating window that is maintained through 10 K program/erase cycles; well controlled array threshold distributions; fast source-side injection programming (10-20 us); fast tunnel erase into the gate; and robust high temperature data retention for both uncycled and cycled arrays. Results presented here with focus on the array operation demonstrate the maturity of this technology for implementation into consumer, industrial, and automotive microcontrollers.
  • Keywords
    NOR circuits; flash memories; integrated memory circuits; memory architecture; microcontrollers; nanostructured materials; nanotechnology; NOR flash memory array; array threshold distributions; automotive microcontrollers; consumer microcontrollers; data retention; industrial microcontrollers; nanocrystal memory; size 90 nm; source side injection programming; time 10 mus to 20 mus; tunnel erase; voltage 1.5 V; Dielectrics; Flash memory; Microcontrollers; Nanocrystals; Nonvolatile memory; Robust control; Silicon; Split gate flash memory cells; Temperature control; Temperature distribution; Data Retention; Endurance; Flash Memories; Memory Array; Microcontrollers; Nanocrystals; Source-side Injection; Tunnel Erase;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 2008 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-1802-2
  • Electronic_ISBN
    978-1-4244-1803-9
  • Type

    conf

  • DOI
    10.1109/VLSIT.2008.4588592
  • Filename
    4588592