A 97mW 0–4GHz 65nm CMOS concurrent receiver

Author

Rivet, Francois ; Deval, Yann

Author_Institution

Univ. of Bordeaux, Bordeaux, France

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

Telecommunication industry claims for an increase of data rate. Techniques must sustain this effort especially by achieving several Gpbs transceivers consumming a very low power. A Sampled Analog Signal Processor was developed performing a Fast Fourier transform using voltage samples to challenge this idea. It receives any RF signal from 0 to 5 GHz, whatever the band and modulation schemes. The circuit was designed in 65nm CMOS technology and demonstrates the feasibility of a concurrent reception within a frequency of 0 to 4GHz at a power consumption of 97mW.

Keywords

CMOS integrated circuits; analogue integrated circuits; fast Fourier transforms; radio transceivers; radiofrequency integrated circuits; signal processing; telecommunication industry; CMOS concurrent receiver; CMOS technology; Gpbs transceivers; RF signal; analog signal processor; band schemes; data rate; fast Fourier transform; frequency 0 GHz to 4 GHz; modulation schemes; power 97 mW; size 65 nm; telecommunication industry; CMOS integrated circuits; Delay lines; Optimization; Power demand; Receivers; Software radio; Synchronization; 5G; RFIC; carrier aggregation; concurrent reception;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021254

Filename

7021254