DocumentCode :
2417219
Title :
Pipelined arithmetic encoder design for lossless JPEG XR encoder
Author :
Ching-Yen Chien ; Sheng-Chieh Huang ; Pan, Chia-Ho ; Ce-Min Fang ; Chen, Liang-Gee
Author_Institution :
Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear :
2009
fDate :
25-28 May 2009
Firstpage :
144
Lastpage :
147
Abstract :
With rapid progress of sensors, display devices, and computing engines, image application exists everywhere. High quality, high compression rates of digital image and low computational cost are important factors of consumer electronics. In this paper, we proposed a 4:4:4 lossless JPEG XR encoder design. In JPEG XR encoder, entropy coding is a critical module of encoder. We proposed a well-defined timing schedule of pipeline architecture to speed up the entropy encoding, which is the most computationally intensive part in JPEG XR encoder. This design can be used for the digital photography applications to achieve the low complexity of computation, low storage, and high dynamic range.
Keywords :
entropy codes; image coding; 4:4:4 lossless JPEG XR encoder design; computing engines; consumer electronics; digital image; digital photography; display devices; entropy coding; high dynamic range; image application; pipelined arithmetic encoder design; sensors; Arithmetic; Computational efficiency; Computer applications; Computer displays; Consumer electronics; Digital images; Engines; Image coding; Image sensors; Transform coding; ASIC; HD-Photo; JPEG XR; encoder;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Consumer Electronics, 2009. ISCE '09. IEEE 13th International Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4244-2975-2
Electronic_ISBN :
978-1-4244-2976-9
Type :
conf
DOI :
10.1109/ISCE.2009.5157025
Filename :
5157025
Link To Document :
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