Integrated circuit interconnect system principal parameter abstract based on neural netwrok

The development of integrated circuit process technology have enabled the single-chip integration of multiple analog and digital function, resulting in complex Systems-on-a-Chip (SoCs). High performance SoC designs have been made feasible by the increased speed and higher density available in nanometer process. A major result of the driver towards ever smaller transistor and interconnect scale is an exponential increase in intra-die and intra-wafer process variations. Process variation has a direct impact on circuit performance. Thus, designers hope than they should evaluate the performance impact based on statistical timing analysis in design stage. However, when the spatial correlation of process parameters is taken into consideration, the parameter correlation structure becomes even more complicated. The paper proposed an integrated circuit interconnect system principal parameter extraction method, which is based on neural network technology. The simulation results prove the method proposed in this paper validity.