DocumentCode :
241865
Title :
Novel CMOS SRAM voltage latched sense amplifiers design based on 65 nm technology
Author :
Zikui Wei ; Xiaohong Peng ; Jinhui Wang ; Haibin Yin ; Na Gong
Author_Institution :
VLSI & Syst. Lab., Beijing Univ. of Technol., Beijing, China
fYear :
2014
fDate :
28-31 Oct. 2014
Firstpage :
1
Lastpage :
3
Abstract :
A novel voltage latched sense amplifier is proposed in this paper. It applies a self-closing bit-line module technique, which makes the input and output nodes separated to optimize sensing delay and power consumption. Initially, the size of transistors in the circuits is adjusted to speed up the circuit and lower the power. The simulation results show that the proposed design improves sensing when smaller bit-lines difference requires for full-swing amplification as the conventional voltage latched sense amplifier. The proposed design also improves power efficiency at least 30% as compared to the conventional voltage latched sense amplifier.
Keywords :
CMOS integrated circuits; SRAM chips; amplifiers; flip-flops; CMOS SRAM voltage latched sense amplifier design; full-swing amplification; power consumption; self-closing bit-line module technique; sensing delay; size 65 nm; Abstracts; Random access memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
Type :
conf
DOI :
10.1109/ICSICT.2014.7021356
Filename :
7021356
Link To Document :
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