Title :
ATGPS using real value logic simulation
Author_Institution :
Univ. of Kitakyushu, Kitakyushu, Japan
Abstract :
In terms of Automatic Test Pattern Generation System, we proposed a new algorithm which employs real value logic simulation, but gate output value calculation method is quite different from Cheng and Agrawal´s in order to realize high fault coverage and process acceleration. Moreover, we implemented our algorithm on parallel processor and could yield high speed processing. Compared with Cheng and Agrawal algorithm, acceleration is about 4× with 100(%) fault coverage. And acceleration is more than 5× using parallel processor moreover.
Keywords :
automatic test pattern generation; logic simulation; parallel processing; ATGPS; Agrawal algorithm; Cheng algorithm; automatic test pattern generation system; gate output value calculation method; high fault coverage; high speed processing acceleration; parallel processor; real value logic simulation; Abstracts; Acceleration; Computers; Fault diagnosis;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021394
