DocumentCode :
2421332
Title :
Global routing in sea-of-gates technology
Author :
Zhou, D.
Author_Institution :
Dept. of Electr. Eng., North Carolina Univ., Charlotte, NC, USA
fYear :
1991
fDate :
10-12 Mar 1991
Firstpage :
359
Lastpage :
362
Abstract :
With the advance of VLSI technology, wires are now routed not only in the channels but also over the cells. The author studies the global routing of multiterminal nets in the sea-of-gates technology. For an m×m array he presents a global router that produces the optimal channel width in the x-direction and guarantees that the channel width in the y-direction is never larger than min(3s*/2,m), where s* is the largest span of the set of nets
Keywords :
VLSI; cellular arrays; circuit layout; integrated circuit technology; network topology; optimisation; 2D array; IC technology; VLSI; global routing; multiterminal nets; sea-of-gates technology; Circuits; Heuristic algorithms; Parallel algorithms; Routing; Simulated annealing; Space technology; Tiles; Very large scale integration; Wires; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System Theory, 1991. Proceedings., Twenty-Third Southeastern Symposium on
Conference_Location :
Columbia, SC
ISSN :
0094-2898
Print_ISBN :
0-8186-2190-7
Type :
conf
DOI :
10.1109/SSST.1991.138580
Filename :
138580
Link To Document :
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