Stacked-cascode Class-E power amplifier with delay-controlled auxiliary branches in 65nm CMOS

Author

Fan Yang ; Yu Liao ; Tao Xia ; Runhua Wang ; Ru Huang ; Huailin Liao

Author_Institution

Lab. of Microelectron. Devices & Circuits, Peking Univ., Beijing, China

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

Low breakdown voltage in deep-submicron CMOS devices has limited the supply voltage and output power of power amplifiers (PAs). In this paper, a differential cascode Class-E PA in 65nm CMOS is proposed. Using only the standard devices, the stacked-cascode structure can endure a maximum voltage up to 10V so that a supply voltage of 3.3V is possible for Class-E PA. An auxiliary branch is added to reduce the turn-on resistance. With an inductor to delay the control signal phase of the branch, the proposed PA has a power dissipation trade-off between the devices´ on/off state. At 1.6GHz, the proposed Class-E PA achieves Power Added Efficiency (PAE) of 57.5% when it transmits 31.3dBm power.

Keywords

CMOS integrated circuits; UHF amplifiers; power amplifiers; CMOS; Class-E power amplifier; frequency 1.6 GHz; inductor; power added efficiency; power dissipation; size 65 nm; turn-on resistance; voltage 10 V; voltage 3.3 V; Breakdown voltage; CMOS integrated circuits; Delays; Inductors; Power amplifiers; Power generation; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021516

Filename

7021516