Title :
Self-repairable EPLDs: design, self-repair, and evaluation methodology
Author :
Lee, Chong H. ; Perkowski, Marek A. ; Hall, Douglas V. ; Jun, David S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Portland State Univ., OR, USA
Abstract :
This paper describes the concept of self-testable and self-repairable EPLDs (Electrically Programmable Logic Devices) for high security and safety applications. A design methodology is proposed for self-repairing of a GAL (Generic Array Logic) which is a kind of EPLD. Our fault-locating and fault-repairing architecture uses universal test sets, fault-detecting logic, and self-repairing circuits with spare devices. The design method allows to detect, diagnose, and repair all multiple stuck-at faults which might occur on E2CMOS cells in programmable AND plane. A “column replacement” method with extra columns is introduced that discards each faulty column entirely and replaces it with an extra column. The evaluation methodology proves that the self-repairable GAL will last longer in the field
Keywords :
automatic testing; logic design; logic testing; programmable logic devices; design methodology; electrically programmable logic devices; evaluation methodology; fault-repairing architecture; generic array logic; multiple stuck-at faults; self-repairable EPLDs; self-testable EPLDs; Built-in self-test; CMOS logic circuits; Circuit faults; Circuit testing; Design methodology; Logic arrays; Logic devices; Logic testing; Programmable logic devices; Security;
Conference_Titel :
Evolvable Hardware, 2000. Proceedings. The Second NASA/DoD Workshop on
Conference_Location :
Palo Alto, CA
Print_ISBN :
0-7695-0762-X
DOI :
10.1109/EH.2000.869356
