An efficient hardware implementation for intra prediction of AVS encoder

This paper describes our techniques to design the intra-prediction of AVS encoder for HDTV applications. The whole design is optimized in both the algorithm and architecture levels. On the algorithm level, since the Plane mode is the most area-costly one, it is temporarily ignored. And SATD is lastly chosen as mode decision to balance the hardware implementation with performance of Rate and Distortion. On the architecture level, in addition to five-parallel system, a new scheduling of encoding process is arranged to avoid the idle cycles together by ping-pong memory architecture between the intra-prediction and entropy coding. As a result, the proposed architecture can be implemented by 11750 Slices, achieves real-time processing of HD(1920times1088) frames at a rate of 30 fps in 100 MHz operation frequency.