Design of dynamic ternary logic using floating-gate MOS transistor

Author

Guoqiang Hang ; Xiaohua Li ; Xiaohui Hu

Author_Institution

Sch. of Inf. & Electr. Eng., Zhejiang Univ., Hangzhou, China

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

A new dynamic circuit scheme to realize voltage-mode ternary circuit using floating-gate MOS (FGMOS) transistor is presented. The dynamic ternary inverter and literal circuits with the less complex structure are designed, and they can be implemented by the standard CMOS process with a double-poly layer without any modification of the thresholds. In the proposed scheme, the circuit output is always brought to logic 1 during the pre-charge phase, to avoid charge sharing in cascaded gates, and then the disadvantage of buffering between stages is eliminated. All the proposed circuits are verified by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology.

Keywords

CMOS integrated circuits; MOSFET; ternary logic; CMOS process; FGMOS transistor; HSPICE simulation; TSMC; cascaded gate; charge sharing; double-polylayer; dynamic circuit scheme; dynamic ternary inverter; dynamic ternary logic design; floating-gate MOS transistor; precharge phase; size 0.35 mum; voltage-mode ternary circuit; Abstracts; CMOS integrated circuits; CMOS technology; Logic gates; Multivalued logic; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021590

Filename

7021590