Title :
Clock gating -A power optimization technique for smart card
Author :
Yongwang Zhou ; Xiaohong Peng ; Ligang Hou ; Peiyuan Wan ; Pingfen Lin
Author_Institution :
Beijing Embedded Syst. Key Lab., Beijing Univ. of Technol., Beijing, China
Abstract :
Power consumption is a key issue of smart card whose power is supplied by induced currents. This paper has described the principle of the clock gating technology which is used to optimize power consumption of the smart card in RTL level. It turns out that the total power consumption has been reduced by 40% using the proposed method, without obvious increase in area. The smart card using the clock gating technology is verified and tested in 180nm process.
Keywords :
optimisation; power aware computing; smart cards; system-on-chip; RTL level; clock gating technology; induced currents; power consumption; power optimization technique; smart card; Abstracts; Clocks; Educational institutions; Flip-flops; Optimization; Smart cards; Switches;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021594
