An area efficient charge pump and a charge pump having adjustable voltage output for embedded nor flash memory

Two charge pumps used for embedded NOR flash memory are introduced in this paper, including an area efficient charge pump and a charge pump having adjustable voltage output. By using poly-poly-substrate (PPS) capacitance and series connection architecture, the area of the charge pump is greatly reduced. By adjusting the voltage output of the charge pump according to the number of cells to be programmed with data “0”, the IR drop on the sourceline (SL) decoding path could be compensated. Thus, a stable SL voltage is obtained and high program efficiency with low program disturb is realized. The function of the two circuits is verified in a 1.8-V 8×8-K-bits embedded NOR flash memory, which was developed on the GSMC 0.18-μm 4-poly 4-metal CMOS process.