DocumentCode :
242478
Title :
Failure mechanisms of guard-drain in mitigating n-hit single-event transient via 45-nm CMOS process
Author :
Xinyu Xu ; Ying Xiong ; Minghua Tang ; Zheng Li ; Yichun Zhou
Author_Institution :
Key Lab. of Low Dimensional Mater. & Applic. Technol. of Minist. of Educ., Xiangtan Univ., Xiangtan, China
fYear :
2014
fDate :
28-31 Oct. 2014
Firstpage :
1
Lastpage :
3
Abstract :
A three-dimensional (3D) technology computer-aided design (TCAD) modeling of guard-drain based on 45-nm CMOS process is presented. Numerical simulations of single-device show that charge collection of the guard-drain technique will higher than that of the conventional technique in different ion incidents. Guard-drain technique fails in helping drain to mitigate single-event transient (SET). Mechanisms of this abnormal phenomenon are analyzed in detail.
Keywords :
CMOS integrated circuits; failure analysis; integrated circuit modelling; numerical analysis; radiation hardening (electronics); technology CAD (electronics); three-dimensional integrated circuits; 3D technology; CMOS process; N-hit single-event transient mitigation; SET; TCAD modeling; charge collection; computer-aided design; guard-drain failure mechanism; ion incident; numerical simulation; size 45 nm; three-dimensional technology; Abstracts; CMOS integrated circuits; CMOS technology; Semiconductor process modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
Type :
conf
DOI :
10.1109/ICSICT.2014.7021663
Filename :
7021663
Link To Document :
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