A behavior modeling method of integrated CMOS Hall element for circuit simulation

A behavior modeling method for Hall element in standard CMOS technology is proposed in this work. Using equivalent parameters, the whole Hall device is represented by lumped circuit elements. The usually concerned factors including mismatch, temperature, stress, and geometry are taken into account in this model. Considering the convenience of integration with following readout and processing circuits, this modeling is set up by items that could be simulated together with other circuits in EDA environment.