Special session 8B: New topic MOS/MTJ-hybrid circuit with nonvolatile logic-in-memory architecture and its impact

Summary form only given. Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. This paper presents novel nonvolatile logic circuits based on logic-in-memory architecture using magnetic tunnel junctions (MTJs) in combination with MOS transistors. Since the MTJ with a spin-injection write capability is only one device that has all the following superior features as large resistance ratio, virtually unlimited endurance, fast read/write accessibility, scalability, complementary MOS (CMOS)-process compatibility, and nonvolatility, it is very suited to implement the MOS/MTJ-hybrid logic circuit with logic-in-memory architecture. As concrete examples of the proposed circuitry, a nonvolatile full adder for motion-vector extraction, a nonvolatile ternary content-addressable memory, and a nonvolatile FPGA, have been proposed. The proposed circuitry also makes it possible to re-program the desired logical threshold of the switching gate even if the transistor characteristics are changed due to the V_th variation. Figure 1 shows the basic structure of the proposed circuitry. The influence of the V_th variation can be neglected by adjusting the source voltage of the MOS transistor. Therefore, the V_th-variation compensation is realized by programming the resistance value of the MTJ device. The usefulness of the proposed compensation circuitry is demonstrated at the comparators as shown in Fig.2. [1] S. Matsunaga, et al., APEX, 1, 9, 091301, Aug. 2008. [2] S. Matsunaga, et al., APEX, 2, 2, 023004, Feb. 2009. [3] D. Suzuki, et al., IEEE 2009 Symposia on VLSI Circuits, 80/81, June 2009.