High-Coupling and Ultra-Low-Loss Interlaced Stacked Transformers for 60-100 GHz CMOS RFIC Applications

In this paper, we demonstrate that high-coupling and ultra-low-loss transformers for 60-100 GHz CMOS RFIC applications can be achieved by using single-turn two-layer interlaced stacked (STIS) structure implemented in a standard CMOS technology. State-of-the-art G _Amax of 0.711, 0.922, and ~1 (i.e. NF_min of 1.48, 0.35, and ~0 dB) were achieved at 60, 80, and 100 GHz, respectively, for a STIS transformer with an inner dimension of 50times50 mu² and a metal width of 5 mum, mainly due to the high magnetic-coupling factor (k_lm) and the high resistive-coupling factor (k_Re). In addition, a 94.1% (from 5.61 to 10.89) and a 196.8% (from 8.36 to 24.81) increase in Q-factor, a 14.2% (from 0.711 to 0.812) and a 8.5% (from 0.922 to ~1) increase in G _Amax, and a 0.58 dB (from 1.48 dB to 0.90 dB) and a 0.35 dB (from 0.35 dB to ~0 dB) decrease in NF_min were achieved at 60 and 80 GHz, respectively, for the transformer after the post-process of proton implantation. The present analysis is helpful for RF engineers to design ultra-low-voltage high-performance 60-100 GHz transformer-feedback CMOS (or BiCMOS) LNAs and VCOs, and other RF-ICs which include transformers