• DocumentCode
    2425345
  • Title

    The roadblocks to broad adoption of high level synthesis

  • Author

    Keating, Mike

  • fYear
    2010
  • fDate
    19-22 April 2010
  • Firstpage
    251
  • Lastpage
    251
  • Abstract
    High level synthesis provides significant benefit to a few users on a few specific problems, most notably video and audio processing. But after more than a decade of use, many users - as well as critics - state that it is not yet ready for wide-spread adoption. This talk discusses why high level synthesis is limited in its appeal and scope, and what must be done to overcome these limitations. In particular, it describes the problems of source language, verification strategy, and the challenges of describing control logic at a high level. It concludes with some suggestions for bridging the gap between high level synthesis and RTL design, and using this as a strategy for overcoming the major roadblocks to broad adoption of high level synthesis.
  • Keywords
    formal verification; hardware description languages; high level synthesis; logic design; RTL design; control logic; high level synthesis; source language; verification strategy; High level synthesis; Logic; Testing; Very large scale integration; Videoconference;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium (VTS), 2010 28th
  • Conference_Location
    Santa Cruz, CA
  • ISSN
    1093-0167
  • Print_ISBN
    978-1-4244-6649-8
  • Type

    conf

  • DOI
    10.1109/VTS.2010.5469567
  • Filename
    5469567