Title :
Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy
Author :
Shamshiri, Saeed ; Cheng, Kwang-Ting
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of California, Santa Barbara, CA, USA
Abstract :
In this paper, we propose a quality metric for an NoC and model the yield and cost of a spare-enhanced multi-core chip subject to a given quality constraint. Our experiments show that the overall quality of a mesh-based NoC depends more on the reliability of the inner links than the outer links; therefore, a non-uniform distribution of spare wires could be more effective and cost efficient than a uniform approach.
Keywords :
costing; network-on-chip; cost; inner links; mesh based NoC; outer links; quality constraint; quality metric; spare wires; spare-enhanced multi-core chip subject; Costs; Field programmable gate arrays; Logic devices; Manufacturing processes; Multicore processing; Network-on-a-chip; Programmable logic arrays; Redundancy; Telecommunication network reliability; Wires; NoC; SoC; non-uniform spare distributtion; quality analysis; yield and cost modeling;
Conference_Titel :
VLSI Test Symposium (VTS), 2010 28th
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-1-4244-6649-8
DOI :
10.1109/VTS.2010.5469579
