Optimized synchronous rectification stage for low output voltage (3.3 V) DC/DC conversion

Author

Cobos, J.A. ; Carcia, O. ; Sebastian, J. ; Uceda, J. ; Aldana, F.

Author_Institution

DIE, Univ. Politecnica de Madrid, Spain

fYear

1994

fDate

20-25 Jun 1994

Firstpage

902

Abstract

A new strategy to obtain low output voltage (3.3 V) is presented in this paper. The output stage is optimized to minimize losses in the self-driven synchronous rectifiers, by means of a fixed frequency, fixed duty cycle (0.5) driving waveform. The output voltage is controlled by a high switching frequency preregulator. This preregulator can be removed if input voltage variation is low. Very high efficiency (93%) has been obtained in an actual prototype (3.3 V and 20 A) of the optimized SR stage

Keywords

DC-DC power convertors; losses; rectification; rectifiers; rectifying circuits; switching circuits; voltage control; 20 A; 3.3 V; 93 percent; DC/DC conversion; fixed duty cycle driving waveform; fixed frequency; high switching frequency preregulator; input voltage variation; losses minimisation; low output voltage; optimized synchronous rectification; output voltage control; self-driven synchronous rectifiers; very high efficiency; Circuit topology; Diodes; Heat sinks; Low voltage; MOSFETs; Pulse width modulation; Rectifiers; Resonance; Strontium; Switching frequency;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Electronics Specialists Conference, PESC '94 Record., 25th Annual IEEE

Conference_Location

Taipei

Print_ISBN

0-7803-1859-5

Type

conf

DOI

10.1109/PESC.1994.373786

Filename

373786