DocumentCode
2425700
Title
Reconfigurable logic gate implemented by suspended-gate single-electron transistors
Author
Sui, Bingcai ; Fang, Liang ; Chi, Yaqing
Author_Institution
Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China
fYear
2010
fDate
20-23 Jan. 2010
Firstpage
26
Lastpage
29
Abstract
As the most attractive candidates for post-CMOS era, single-electronic transistors (SETs) can potentially deliver high device density and power efficiency at good speed. SET with suspended-gate has many more unique merits. Reconfigurable logic gate based on suspended-gate SET is designed, which can efficiently make use of the tunable coulomb oscillation and NEMS gate capacitances. The simulation result shows that the reconfigurable cell based on suspended-gate SET can flexibly realize many more functions at room temperature with high performance at much lower cost of area and power, and be very useful for the logic design based on suspended-gate SETs to construct some more efficient structures(e.g. FPGA, programmable architecture, and so on).
Keywords
CMOS integrated circuits; capacitance; circuit oscillations; logic design; logic gates; nanoelectromechanical devices; single electron transistors; NEMS gate capacitance; high device density; logic design; post-CMOS era; power efficiency; reconfigurable cell; reconfigurable logic gate; suspended-gate SET; suspended-gate single-electron transistor; tunable coulomb oscillation;
fLanguage
English
Publisher
ieee
Conference_Titel
Nano/Micro Engineered and Molecular Systems (NEMS), 2010 5th IEEE International Conference on
Conference_Location
Xiamen
Print_ISBN
978-1-4244-6543-9
Type
conf
DOI
10.1109/NEMS.2010.5592136
Filename
5592136
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