Title :
Path clustering for adaptive test
Author :
Uezono, Takumi ; Takahashi, Tomoyuki ; Shintani, Michihiro ; Hatayama, Kazumi ; Masu, Kazuya ; Ochi, Hiroyuki ; Sato, Takashi
Author_Institution :
Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama, Japan
Abstract :
Adaptive test is one of the most efficient techniques that practically ensure high yield and reliability of designed chips. In this paper, a novel path-clustering method suitable for the adaptive test, in which test paths are altered according to the monitored process-parameters, is proposed. Considering the probability function of the die-to-die systematic process variation, the proposed method clusters path sets so that the total number of test-paths are minimized. For quantitative evaluation of different clusterings, figure of merit for clustering, which represents the expected number of test-paths at a particular test coverage, is also proposed. The proposed clustering is experimentally evaluated by applying to an industrial circuit. With our clustering, the average test paths in the adaptive test have been reduced to less than 50% compared with the ones of the conventional test.
Keywords :
integrated circuit testing; pattern clustering; adaptive test technique; average test paths; die-to-die systematic process variation; industrial circuit; path clustering method; probability function; Circuit faults; Circuit synthesis; Circuit testing; Clustering algorithms; Delay; Semiconductor device measurement; Semiconductor device testing; System testing; Timing; Very large scale integration;
Conference_Titel :
VLSI Test Symposium (VTS), 2010 28th
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-1-4244-6649-8
DOI :
10.1109/VTS.2010.5469626