Title :
Algorithm features of hierarchical descending placement
Abstract :
In clause the description of descending hierarchical placement algorithm and influence of realization variants on placement results is carried out. The research is carried out on the basis of real constructives.
Keywords :
circuit complexity; circuit layout CAD; parallel algorithms; algorithm realizations; binary tree; complexity; connectivities between elements; consecutive escalating; design automation; hierarchical descending placement; hierarchical placement algorithm; internal connections; macromodels; optimum convolution tree; parallel-sequential algorithms; parameters change influence; Circuits; Convolution; Terminology;
Conference_Titel :
CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference. The Experience of Designing and Application of
Print_ISBN :
966-553-278-2
DOI :
10.1109/CADSM.2003.1255067
