Title :
A configurable architecture for smart pixel research
Author :
Cantin, J.F. ; Beyette, F.R., Jr.
Author_Institution :
Dept. of Electr. Comput. Eng. & Comput. Sci., Cincinnati Univ., OH, USA
Abstract :
We propose a general purpose, smart pixel based photonic information processing architecture comprised of RISC processing pixels and a reconfigurable micro instruction store. Implemented with a photonic VLSI technology the device is suitable for prototyping photonic information processing systems.
Keywords :
CMOS integrated circuits; VLSI; optical logic; parallel architectures; reconfigurable architectures; reduced instruction set computing; smart pixels; CASPR architecture; RISC processing pixels; SIMD; configurable architecture; general purpose architecture; photonic VLSI technology; photonic information processing architecture; reconfigurable micro instruction store; smart pixel; CMOS logic circuits; Computer aided instruction; Computer architecture; Information processing; Optical arrays; Optical computing; Optical devices; Photonics; Smart pixels; Very large scale integration;
Conference_Titel :
Electronic-Enhanced Optics, Optical Sensing in Semiconductor Manufacturing, Electro-Optics in Space, Broadband Optical Networks, 2000. Digest of the LEOS Summer Topical Meetings
Conference_Location :
Aventura, FL, USA
Print_ISBN :
0-7803-6252-7
DOI :
10.1109/LEOSST.2000.869702
